The exercises refer to the course book.
Refer to time edit for time and room of the exercises!
Questions E5. You should look for the answers in the distributed manual.
- How many pipeline stages are there for an integer (i.e. fixed-point) arithmetic instruction?
- Same for floating-point instruction?
- What does instruction cracking mean and why is it done?
- Instructions are dispatched from the dispatch buffer in groups of up to five instructions. Which instruction type does always end a group? For example, if the third instruction is of that type, the group will contain only three instructions.
- How many instructions can be in the reorder buffer at the same time (the reorder buffer is called Global Completion Table)?
- What is a rename register and how many integer and floating point rename register does the 970MP have in each processor?
- How many more clock cycles does it take to use a floating point operand read from the cache compared to an integer operand read from the cache?
- How many floating point add instructions can the 970MP start executing each clock cycle?
|E1||1.2.1, 1.2.2, 1.2.7, 1.4.2, 1.4.3|
|E2||1.4.5, 1.4,6, 1.4.7, 1.4.8, 1.4.12|
|E3||3.4.1, 3.4.2, 3.4.3, 3.4.4, 3.4.5, 3.4.6, 3.4.8|
|E4||4.7.1, 4.7.2, 4.7.3, 4.7.4|
Superscalar instruction execution.
|E6||12.1.1, 12.1.4, 14.4.1, 14.6.1,|